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HT82A832R Basic USB Phone OTP MCU
Features
* Operating voltage: fSYS = 6M/12MHz: 4.0V~5.5V * 24 bidirectional I/O lines (max.) * Two 16-bit programmable timer/event counters and * Two hardware implemented Isochronous transfers * Total FIFO size: 464 bytes
(8, 8, 384, 32, 32 for EP0~EP4)
* Programmable frequency divider (PFD) * Integrated SPI hardware circuit * Play/Record Interrupt * HALT and wake-up features reduce power
overflow interrupts
* 409615 program memory ROM * 1928 data memory RAM (Bank 0) * USB 2.0 full speed compatible * USB spec V1.1 full speed operation and USB audio
consumption
* Watchdog Timer * 16-level subroutine nesting * Bit manipulation instruction * 15-bit table read instruction * 63 powerful instructions * All instructions executed within one or two machine
device class spec V1.0
* Embedded high-performance 16 bit PCM ADC * Built-in Digital PGA (Programmable Gain Amplifier) * 48kHz/8kHz sampling rate for audio playback
controlled by software option
* 8kHz audio recording sampling rate * Embedded class AB speaker driver power amplifier * Embedded High Performance 16 bit audio DAC * Supports audio playback digital volume control * 5 endpoints supported (endpoint 0 included) * Supports 1 Control, 2 Interrupt, 2 Isochronous
cycles
* Low voltage reset function (3.0V0.3V) * 48-pin SSOP/LQFP package
transfer
General Description
The HT82A832R is an 8-bit high performance RISC-like microcontroller designed for USB Phone product applications. The HT82A832R combines a 16-bit PCM ADC, USB transceiver, SIE (Serial Interface Engine), audio class processing unit, FIFO and an 8-bit MCU into a single chip. The DAC in the HT82A832R operates at a sampling rate of 48kHz/8kHz and the 16-bit PCM ADC operates at 8kHz for the Microphone input. For the DAC, the HT82A832R has a digital programmable gain amplifier. The gain range is from -32dB to +6dB. For the ADC input, the digital gain range is from 0dB to 19.5dB.
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HT82A832R
Block Diagram
STACK0 STACK1 STACK2 STAC K14 P ro g ra m ROM P ro g ra m C o u n te r STAC K15 IN T C TM R0 M U X In s tr u c tio n R e g is te r TM R0C MP M U X DATA M e m o ry W DTS W D T P r e s c a le r In s tr u c tio n D ecoder ALU T im in g G e n e ra to r S h ifte r MUX PAC STATUS PA PBC PB PCC PC U S B 1 .1 X C V R PORT C PORT B PORT A PA0~PA7 W DT M U X fS /4 BP In te rru p t C ir c u it TM R1C M U X TM R1 fS
YS
/4 P C 1 /T M R 0
YS
P C 2 /T M R 1
E N /D IS fS
YS
/4
W DT OSC
PB0~PB7
OSCO USBDP USBDN V33O
OSCI
ACC
PC3 M U X
U S B 1 .1 F u ll S p e e d E n g in e
S e r ia l In te rfa c e PFD
PC 4~PC 7 (S D O , S D I, S C S , S C K ) P C 0 /B Z
3 .3 V R e g u la to r F IF O
IS O P ro c e s s
AVSS3 VAG Ref VAG TG T IT I+ AVDD3 1 6 - b it D /A M U X Power Amp LO UT ROUT M U S IC _ IN 1 6 - b it A /D C o n v e rte r D ig ita l PGA D A C W r ite D a ta D ig ita l V o lu m e C o n tro l
MUX
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HT82A832R
Pin Assignment
PA3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PA2 PA1 PA0 AVDD2 ROUT LO UT AVSS2 AVSS1 B IA S M U S IC _ IN AVDD1 AVDD3 VAG R ef VAG T I+ T ITG AVSS3 PB7 PB6 PB5 PB4 DVSS2 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 PA4 PA5 PA6 PA7 DVSS1 V33O USBDP USBDN DVDD1 RESET OSCO OSCI P C 0 /B Z P C 1 /T M R 0 P C 2 /T M R 1 PC3 P C 4 /S D O P C 5 /S D I P C 6 /S C S P C 7 /S C K PB0 PB1 PB2 PB3 ROUT LO UT AVSS2 AVSS1 B IA S M U S IC _ IN AVDD1 AVDD3 VAG R ef VAG T I+ T I1 2 3 4 5 6 7 8 9 10 11 12 131415161718192021222324 HT82A832R 4 8 L Q F P -A USBD V33 DVSS PA PA PA PA PA PA PA PA AVDD O P 484746454443424140393837 2 0 1 2 3 4 5 6 7 1 36 35 34 33 32 31 30 29 28 27 26 25 USBDN DVDD1 RESET OSCO OSCI P C 0 /B Z P C 1 /T M P C 2 /T M PC3 P C 4 /S D P C 5 /S D P C 6 /S C S R0 R1 I O PC PB PB PB PB DV PB PB PB PB AV TG 7 /S C K 0 1 2 3 SS2 4 5 6 7 SS3
HT82A832R 4 8 S S O P -A
Pin Description
Pin Name PA0~PA7 AVDD2 ROUT LOUT AVSS2 AVSS1 BIAS MUSIC_IN AVDD1 AVDD3 VAGRef VAG TI+ TITG I/O I/O 3/4 O O 3/4 3/4 3/4 I 3/4 3/4 O O I I O Description Bidirectional 8-bit input/output port. Each bit can be configured as a wake-up input by a configuration option. Software instructions determine if the pin is a CMOS output or Schmitt trigger input with or without a pull-high resistor (by configuration option). Audio power amplifier positive power supply Right driver analog output Left driver analog output Audio power amplifier negative power supply, ground Audio DAC negative power supply, ground A capacitor should be connected to ground to increase half-supply stability Power amplifier signal source if register bit SELW =1. The analog signal input will amplify by the power amp then output to ROUT and LOUT at the same time. Audio DAC positive power supply ADC positive power supply ADC analog ground reference voltage (should left open or connect a bypass capacitor (Ex:100 pF) to ground) ADC analog ground voltage (should connect a bypass capacitor (Ex:1 uF) to ground) OP AMP non-inverting input OP AMP inverting input OP AMP gain setting output
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Pin Name AVSS3 PB7~PB0 DVSS2 PC7/SCK PC6/SCS PC5/SDI PC4/SDO PC3 PC2/TMR1, PC1/TMR0 PC0/BZ OSCI OSCO RESET DVDD1 USBDN USBDP V33O DVSS1 I/O 3/4 I/O 3/4 I/O I/O I/O or I ADC negative power supply, ground Bidirectional 8-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt trigger input with pull-high resistor (determined by pull-high options, bit option). Negative digital & I/O power supply, ground Can be software optioned as a bidirectional input/output or serial interface clock signal. Can be software optioned as a bidirectional input/output or serial interface slave select signal. Can be software optioned as a bidirectional input/output or serial data input. Description
I/O Can be software optioned as a bidirectional input/output or serial data output. or O I/O I/O Bidirectional I/O lines. Software instructions determine if the pin is a CMOS output or Schmitt trigger input with pull-high resistor (determined by configuration option). Software instructions determine if the pin is a CMOS output or Schmitt trigger input with pull-high resistor. TMR0, TMR1 are pin shared with PC1, PC2 respectively
I/O Can be software optioned as a bidirectional input/output or as a PFD output. or O I O I 3/4 I/O I/O O 3/4 OSCI, OSCO are connected to an 6MHz or 12MHz crystal/resonator (determined by software instructions) for the internal system clock Schmitt trigger reset input, active low Positive digital power supply USBD- line. The USB function is controlled by a software control register USBD+ line. The USB function is controlled by a software control register 3.3V regulator output Negative digital power supply, ground
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V Input Voltage..............................VSS-0.3V to VDD+0.3V Storage Temperature ............................-50C to 125C Operating Temperature...........................-40C to 85C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
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D.C. Characteristics
Symbol VDD Parameter Operating Voltage Test Conditions VDD 5V 5V IDD Operating Current 5V Conditions 3/4 No load, fSYS=12MHz, ADC On, DAC On No load, fSYS=12MHz, ADC Off, DAC Off No load, system HALT, USB transceiver and 3.3V regulator on 3/4 3/4 3/4 3/4 VOL=0.1VDD VOH=0.7VDD 3/4 3/4 IV33O=-5mA Min. 4.0 3/4 3/4 3/4 0 0.7VDD 0 0.9VDD 3/4 3/4 30 2.7 3.0 Typ. 5.0 12 8 Max. 5.5 3/4 3/4 3/4 0.3VDD VDD 0.4VDD VDD 3/4 3/4 80 3.3 3.6 Ta=25C Unit V mA mA mA V V V V mA mA kW V V
ISUS VIL1 VIH1 VIL2 VIH2 IOL IOH RPH VLVR VV33O
Suspend Current Input Low Voltage for I/O Ports Input High Voltage for I/O Ports Input Low Voltage (RESET) Input High Voltage (RESET) I/O Port Sink Current I/O Port Source Current Pull-high Resistance Low Voltage Reset 3.3V Regulator Output
5V 5V 5V 5V 5V 5V 5V 5V 5V 5V
330 3/4 3/4 3/4 3/4 5 -5 40 3.0 3.3
DAC+Power Amp: Test condition: Measurement bandwidth 20Hz to 20kHz, fS= 48kHz. Line output series capacitor with 220mF. THD+N THD+NNote1 Signal to Noise RatioNote1 5V 4W load 8W load SNRDA 5V 4W load 8W load Dynamic Range 5V 4W load 8W load POUT Output Power 5V 4W load, THD=10% 8W load, THD=10% 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 -30 -35 81 82 87 88 400 200 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 dB
dB
DR
dB
mW/ch
PCM ADC SNRAD VAG VPEAK Signal to Noise Ratio Reference Voltage Peak Single Frequency Tone Amplitude without Clipping 5V 5V 5V 77 2 1.575 dB V VPK
Note.1: Sine wave input at 1kHz, -6dB
A.C. Characteristics
Symbol fSYS Parameter System Clock (Crystal OSC) Test Conditions VDD 5V 5V 3/4 3/4 3/4 Conditions 3/4 3/4 3/4 3/4 3/4 Min. 0.4 3/4 1 3/4 1 Typ. 3/4 100 3/4 1024 3/4 Max. 12 3/4 3/4 3/4 3/4
Ta=25C Unit MHz ms ms tSYS ms
tWDTOSC Watchdog Oscillator Period tRES tSST tINT RESET Input Pulse Width System Start-up Timer Period Interrupt Pulse Width
Note: tSYS=1/fSYS Rev. 1.00 5 July 18, 2006
HT82A832R
Functional Description
Execution Flow The system clock for the microcontroller is sourced from a crystal oscillator. The system clock is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruction to be effectively executed in a cycle. If an instruction changes the program counter, two cycles are required to complete the instruction. Program Counter - PC The program counter (PC) controls the sequence in which the instructions stored in the program ROM are executed and its contents specify a full range of program memory.
T1 T2 T3 T4 T1 T2
After accessing a program memory word to fetch an instruction code, the contents of the program counter are incremented by one. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip execution, loading to the PCL register, performing a subroutine call or return from subroutine, initial reset, internal interrupt, external interrupt or return from interrupts, the PC manipulates the program transfer by loading the address corresponding to each instruction. The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise proceed with the next instruction. The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into
T3 T4 T1 T2 T3 T4
S y s te m
C lo c k
O S C 2 ( R C o n ly ) PC PC PC+1 PC+2
F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 )
Execution Flow
Mode Initial Reset USB Interrupt Timer/Event Counter 0 Overflow Timer/Event Counter 1 Overflow Play Interrupt Serial Interface Interrupt Record Interrupt Skip Loading PCL Jump, Call Branch Return from Subroutine
Program Counter *11 0 0 0 0 0 0 0 *10 0 0 0 0 0 0 0 *9 0 0 0 0 0 0 0 *8 0 0 0 0 0 0 0 *7 0 0 0 0 0 0 0 *6 0 0 0 0 0 0 0 *5 0 0 0 0 0 0 0 *4 0 0 0 0 1 1 1 *3 0 0 1 1 0 0 1 *2 0 1 0 1 0 1 0 *1 0 0 0 0 0 0 0 *0 0 0 0 0 0 0 0
Program Counter+2 *11 #11 S11 *10 #10 S10 *9 #9 S9 *8 #8 S8 @7 #7 S7 @6 #6 S6 @5 #5 S5 @4 #4 S4 @3 #3 S3 @2 #2 S2 @1 #1 S1 @0 #0 S0
Program Counter Note: *11~*0: Program counter bits #11~#0: Instruction code bits Rev. 1.00 6 S11~S0: Stack register bits @7~@0: PCL bits July 18, 2006
HT82A832R
the PCL performs a short jump. The destination will be within the current program ROM page. When a control transfer takes place, an additional dummy cycle is required. Program Memory - PROM The program memory is used to store the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 409615 bits, addressed by the program counter and table pointer. Certain locations in the program memory are reserved for special usage:
* Location 000H * Location 018H
This area is reserved for the record interrupt service program. If the record data valid, the interrupt is enabled and the stack is not full, the program begins execution at location 018H.
* Table location
Any location in the program memory can be used as a look-up table. There are three methods to read the ROM data using two table read instructions: TABRDC and TABRDL, transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H). The three methods are shown as follows:
This area is reserved for program initialization. After a chip reset, the program always begins execution at location 000H.
* Location 004H
The instruction TABRDC [m] (the current page, one page=256 words), where the table location is defined by TBLP (07H) in the current page. The configuration option, TBHP, is disabled (default). The instruction TABRDC [m], where the table location is defined by registers TBLP (07H) and TBHP (01FH). The configuration option, TBHP, is enabled. The instruction TABRDL [m], where the table locations is defined by register TBLP (07H) in the last page (0F00H~0FFFH).
D e v ic e In itia liz a tio n P r o g r a m U S B In te r r u p t S u b r o u tin e T im e r /E v e n t C o u n te r 0 In te r r u p t S u b r o u tin e T im e r /E v e n t C o u n te r 1 In te r r u p t S u b r o u tin e P la y In te r r u p t S u b r o u tin e S e r ia l In te r fa c e In te r r u p t S u b r o u tin e R e c o r d In te r r u p t S u b r o u tin e P ro g ra m M e m o ry
This area is reserved for the USB interrupt service program. If the USB interrupt is activated, the interrupt is enabled and the stack is not full, the program begins execution at location 004H.
* Location 008H
000H 004H 008H 00CH 010H 014H 018H
This area is reserved for the Timer/Event Counter 0 interrupt service program. If a timer interrupt results from a Timer/Event Counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 008H.
* Location 00CH
This area is reserved for the Timer/Event Counter 1 interrupt service program. If a timer interrupt results from a Timer/Event Counter 1 overflow, and the interrupt is enabled and the stack is not full, the program begins execution at location 00CH.
* Location 010H
This area is reserved for the play interrupt service program. If play data is valid, and the interrupt is enabled and the stack is not full, the program begins execution at location 010H.
* Location 014H
n00H nFFH
L o o k - u p T a b le ( 2 5 6 w o r d s )
F00H FFFH
L o o k - u p T a b le ( 2 5 6 w o r d s ) 1 5 b its N o te : n ra n g e s fro m 1 to F
This area is reserved for when 8 bits of data have been received or transmitted successfully from the serial interface. If the related interrupts are enabled, and the stack is not full, the program begins execution at location 014H. Instruction TABRDC [m] TABRDL [m]
Program Memory
Table Location *11 P11 1 *10 P10 1 *9 P9 1 *8 P8 1 *7 @7 @7 *6 @6 @6 *5 @5 @5 *4 @4 @4 *3 @3 @3 *2 @2 @2 *1 @1 @1 *0 @0 @0
Table Location Note: *11~*0: Table location bits P11~P8: Current program counter bits TBHP register bit3~bit0 when TBHP is enabled Rev. 1.00 7 July 18, 2006 P11~P8: Current program counter bits when TBHP is disabled @7~@0: Table pointer bits
HT82A832R
Only the destination of the lower-order byte in the table is well-defined, the other bits of the table word are transferred to the lower portion of TBLH, and the remaining 1-bit words are read as 0. The Table Higher-order byte register (TBLH) is read only. The table pointer (TBLP, TBHP) is a read/write register (07H, 1FH), which indicates the table location. Before accessing the table, the location must be placed in the TBLP and TBHP registers. (If the configuration option TBHP is disabled, the value in TBHP has no effect). TBLH is read only and cannot be restored. If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine is likely to be changed by the table read instruction used in the ISR. As a result errors may occur. In other words, using the table read instruction in the main routine and in the ISR simultaneously should be avoided. However, if the table read instruction has to be applied in both the main routine and the ISR, the interrupt should be disabled prior to the table read instruction. It will not be enabled until the TBLH has been backed up. All table related instructions require two cycles to complete the operation. These areas may function as n o rm a l p r ogr a m m em or y d e p e n d i ng o n t h e requirements. Once the TBHP is enabled, the instruction TABRDC [m] reads the ROM data as defined by the TBLP and TBHP register value. Otherwise, if the configuration option TBHP is disabled, the instruction TABRDC [m] reads the ROM data as defined by TBLP and the current program counter bits. Stack Register - STACK This is a special part of the memory which is used to save the contents of the program counter only. The stack is organized into 16 levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the stack pointer (SP) and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction (RET or RETI), the program counter is restored to its previous value from the stack. After a chip reset, the stack pointer will point to the top of the stack. If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the stack pointer is decremented (by RET or RETI), the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. In a similar case, if the stack is full and a CALL is subsequently executed, stack overflow occurs and the first entry will be lost (only the most recent 16 return addresses are stored). Rev. 1.00 8 Data Memory - RAM The data memory is divided into two functional groups: namely; special function registers and general purpose data memory, Bank 0: 1928 bits. Most are read/write, but some are read only. The special function registers include the indirect addressing registers (R0;00H, R1;02H), Bank register (BP;04H), Timer/Event Counter 0 higher order byte register (TMR0H;0CH), Timer/Event Counter 0 lower order byte register (TMR0L;0DH), Timer/Event Counter 0 control register (TMR0C;0EH), Timer/Event Counter 1 higher order byte register (TMR1H;0FH), Timer/Event Counter 1 lower order byte register (TMR1L;10H), Timer/Event Counter 1 control register (TMR1C;11H), program counter lower-order byte register (PCL;06H), memory pointer registers (MP0;01H, MP1;03H), accumulator (ACC;05H), table pointer (TBLP;07H, TBHP;1FH), table higher-order byte register (TBLH;08H), status register (STATUS;0AH), interrupt control register0 (INTC0;0BH), Watchdog Timer option setting register (WDTS;09H), I/O registers (PA;12H, PB;14H, PC;16H), I/O control registers (PAC;13H, PBC;15H, PCC;17H). Digital Volume Control Register (USVC;1CH). USB status and control register (USC;20H), USB endpoint interrupt status register (USR;21H), system clock control register (UCC;22H). Address and remote wakeup register (AWR;23H), STALL register (24H), SIES register (25H), MISC register (26H), SETIO register (27H). FIFO0~FIFO4 register (28H~2CH). DAC_Limit_L register (2DH), DAC_Limit_H register (2EH), DAC_WR register (2FH). PGA_CTRL register (30H). PFD control register (PFDC;31H). PFD data register (PFDD;32H). MODE_CTRL register (34H). Serial bus control register (SBCR;35H), serial bus data register (SBDR;36H). Play data left channel (PLAY_DATAL_L;3AH, PLAY_DATAL_H;3BH), play data right channel (PLAY_DATAR_L;3CH, PLAY_ DATAR_H;3DH). Record data (RECORD_DATA_L; 3EH, RECORD_DATA_H; 3FH). The remaining space before the 40H is reserved for future expanded usage, reading these locations will return a result of 00H. The general purpose data memory, addressed from 40H to FFH, is used for data and control information under instruction commands. All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and reset by SET [m].i and CLR [m].i. They are also indirectly accessible through memory pointer registers (MP0 or MP1).
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00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H B a n k 0 S p e c ia l R e g is te r In d ir e c t A d d r e s s in g R e g is te r 0 MP0 In d ir e c t A d d r e s s in g R e g is te r 1 MP1 BP ACC PCL TBLP TBLH W DTS STATUS IN T C 0 TM R0H TM R0L TM R0C TM R1H TM R1L TM R1C PA PAC PB PBC PC PCC
Indirect Addressing Register Locations 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write operation on [00H] ([02H]) will access the data memory pointed to by MP0 (MP1). Reading location 00H (02H) indirectly will return the result 00H. Writing indirectly results in no operation. The function of data movement between two indirect addressing registers is not supported. The memory pointer registers (MP0 and MP1) are 8-bit registers used to access the RAM by combining corresponding indirect addressing registers. Bank Pointer The bank pointer is used to assign the accessed RAM bank. When the users want to access the RAM bank 0, a 0 should be loaded onto BP. RAM locations before 40H in any bank are overlapped. Accumulator The accumulator is closely related to ALU operations. It is also mapped to location 05H of the data memory and can carry out immediate data operations. The data movement between two data memory locations must pass through the accumulator.
S p e c ia l P u r p o s e D a ta M e m o ry
USVC IN T C 1 TBHP USC USR UCC AW R STALL S IE S M IS C S E T IO F IF O 0 F IF O 1 F IF O 2 F IF O 3 F IF O 4 D A C _ L IM IT _ L D A C _ L IM IT _ H DAC_W R PG A_CTRL PFDC PFDD M O DE_CTRL SBCR SBDR
Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic operations. The ALU provides the following functions:
* Arithmetic operations (ADD, ADC, SUB, SBC, DAA) * Logic operations (AND, OR, XOR, CPL) * Rotation (RL, RR, RLC, RRC) * Increment and Decrement (INC, DEC) * Branch decision (SZ, SNZ, SIZ, SDZ ....)
The ALU not only saves the results of a data operation but also changes the status register. Status Register - STATUS This 8-bit register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). It also records the status information and controls the operation sequence. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results from those intended. The TO flag can be affected only by a system power-up, a WDT time-out or executing the CLR WDT or HALT instruction. The Z, OV, AC and C flags generally reflect the status of the latest operations.
PLAY PLAY PLAY PLAY RECO RECO
_D _D _D _D RD RD
AT AT AT AT _D _D
AL AL AR AR AT AT
_L _H _L _H A_L A_H :U nused R e a d a s "0 0 "
FFH
G e n e ra l P u rp o s e D a ta R A M (1 9 2 B y te s )
RAM Mapping Rev. 1.00 9 July 18, 2006
HT82A832R
Bit No. 0 Label C Function C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared. OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. PDF is cleared by a system power-up or executing the CLR WDT instruction. PDF is set by executing the HALT instruction. TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. Unused bit, read as 0 Status (0AH) Register In addition, upon entering the interrupt sequence or executing a subroutine call, the status register will not be automatically pushed onto the stack. If the contents of the status are important and if the subroutine can corrupt the status register, precautions must be taken to save it properly. Interrupt The device provides a USB interrupt, internal timer/event counter interrupts, play/record data valid interrupt and a serial interface interrupt. The Interrupt Control Register0 (INTC0;0BH) and interrupt control register1 (INTC1;1EH) both contain the interrupt control bits that are used to set the enable/disable status and interrupt request flags. Once an interrupt subroutine is serviced, all the other interrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may occur during this interval but only the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the EMI bit and the corresponding bit of the INTC0 or INTC1 may be set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. All these kinds of interrupts have a wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at specified location in the program memory. Only the program counter is pushed onto the stack. If the contents of the register or status register (STATUS) are altered by the interrupt service program which corrupts the desired control sequence, the contents should be saved in advance. The USB interrupts are triggered by the following USB events and the related interrupt request flag (USBF; bit 4 of the INTC0) will be set.
* Accessing the corresponding USB FIFO from the PC * The USB suspend signal from the PC * The USB resume signal from the PC * USB Reset signal
1 2 3 4 5 6~7
AC Z OV PDF TO 3/4
When the interrupt is enabled, the stack is not full and the USB interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag (USBF) and EMI bits will be cleared to disable other interrupts. When the PC Host accesses the FIFO of the HT82A832R, the corresponding request bit of the USR is set, and a USB interrupt is triggered. So the user can easily determine which FIFO has been accessed. When the interrupt has been served, the corresponding bit should be cleared by firmware. When the HT82A832R receives a USB Suspend signal from the Host PC, the suspend line (bit0 of USC) of the HT82A832R is set and a USB interrupt is also triggered. Also when the HT82A832R receives a Resume signal from the Host PC, the resume line (bit3 of USC) of the HT82A832R is set and a USB interrupt is triggered. The internal Timer/Event Counter 0 interrupt is initialized by setting the Timer/Event Counter 0 interrupt request flag (bit 5 of INTC0), caused by a timer 0 overflow. When the interrupt is enabled, the stack is not full and the T0F bit is set, a subroutine call to location 08H will occur. The related interrupt request flag (T0F) will be reset and the EMI bit cleared to disable further interrupts. The internal Timer/Event counter 1 interrupt is initialized by setting the Timer/Event Counter 1 interrupt request flag (bit 6 of INTC0), caused by a timer 1 overflow. When the interrupt is enabled, the stack is not full and T1F is set, a subroutine call to location 0CH will occur. The
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Bit No. 0 1 2 3 4 5 6 7 Label EMI EUI ET0I ET1I USBF T0F T1F 3/4 Function Controls the master (global) interrupt (1=enable; 0=disable) Controls the USB interrupt (1=enable; 0=disable) Controls the Timer/Event Counter 0 interrupt (1=enable; 0=disable) Controls the Timer/Event Counter 1 interrupt (1=enable; 0=disable) USB interrupt request flag (1=active; 0=inactive) Internal Timer/Event Counter 0 request flag (1=active; 0=inactive) Internal Timer/Event Counter 1 request flag (1=active; 0=inactive) Unused bit, read as 0 INTC0 (0BH) Register Bit No. 0 1 2 3, 7 4 5 6 Label EPLAYI ESII RECI 3/4 PLAYF SIF RECF Play interrupt (1=enable; 0=disable) Control Serial interface interrupt (1=enable; 0=disable) Record interrupt (1=enable; 0=disable) Unused bit, read as 0 Play interrupt request flag (1=active; 0=inactive) Serial interface interrupt request flag (1=active; 0=inactive) Record interrupt request flag (1=active; 0=inactive) INTC1 (1EH) Register related interrupt request flag (T1F) will be reset and the EMI bit cleared to disable further interrupts. The play interrupt is initialized by setting the play interrupt request flag (bit 4 of INTC1), caused by a play data valid. When the interrupt is enabled, the stack is not full and the PLAYF is set, a subroutine call to location 10H will occur. The related interrupt request flag (PLAYF) will be reset and the EMI bit cleared to disable further interrupts. If PLAY_MODE (bit 3 of MODE_CTRL register) is set to 1, the play interrupt frequency will change to 8KHz, otherwise the interrupt frequency is 48kHz. The serial interface interrupt is indicated by the interrupt flag (SIF; bit 5 of INTC1), that is generated by the reception or transfer of a complete 8-bits of data between the HT82A832R and the external device. The serial interface interrupt is controlled by setting the Serial interface interrupt control bit (ESII; bit 1 of INTC1). After the interrupt is enabled (by setting SBEN; bit 4 of SBCR), and the stack is not full and the SIF is set, a subroutine call to location 14H occurs. The record interrupt is initialized by setting the record interrupt request flag (bit 6 of INTC1), caused by a record data valid. When the interrupt is enabled, the stack is not full and RECF is set, a subroutine call to location 18H will occur. The related interrupt request flag (RECF) will be reset and the EMI bit cleared to disable further interrupts. If ADC powered down (AD_ENB =1) or USB clock disabled (USBCKEN=0), the record interrupt will be disabled. During the execution of an interrupt subroutine, other interrupt acknowledge signals are held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are set to 1 (if the stack is not full). To return from the interrupt subroutine, RET or RETI may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not. Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests the following table shows the priority that is applied. These can be masked by resetting the EMI bit. Interrupt Source USB interrupt Timer/Event Counter 0 overflow Timer/Event Counter 1 overflow Play Interrupt Serial Interface Interrupt Record Interrupt Priority 1 2 3 4 5 6 Vector 04H 08H 0CH 10H 14H 18H Function
It is recommended that a program does not use the CALL subroutine within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and enabling the interrupt is not well controlled, the original control sequence will be damaged once the CALL operates in the interrupt subroutine. 11 July 18, 2006
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Oscillator Configuration The microcontroller contains an integrated oscillator circuit.
OSCI
(system clock/4). The timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. The WDT can be disabled by a configuration option. However, if the WDT is disabled, all executions related to the WDT lead to no operation. When the WDT clock source is selected, it will be first divided by 256 (8-stage) to get the nominal time-out period. By invoking the WDT prescaler, longer time-out periods can be realized. Writing data to WS2, WS1, WS0 can give different time-out periods. The WDT OSC period is typically 65ms. This time-out period may vary with temperature, VDD and process variations. The WDT OSC always keeps running in any operation mode. If the instruction clock is selected as the WDT clock source, the WDT operates in the same manner except in the halt mode. In the HALT mode, the WDT stops counting and lose its protecting purpose. In this situation the logic can only be re-started by external logic. The high nibble of the WDTS is reserved for the DAC write mode. The WDT overflow under normal operation initializes a chip reset and sets the status bit TO. In the HALT mode, the overflow initializes a warm reset, and only the program counter and stack pointer are reset to zero. To clear the contents of the WDT, there are three methods to be adopted, i.e., an external reset (a low level to RESET), a software instruction, and a HALT instruction. There are two types of software instructions; Function
OSCO C r y s ta l O s c illa to r
System Oscillator This oscillator is designed for the system clock. The HALT mode stops the system oscillator and ignores any external signals to conserve power. A crystal across OSCI and OSCO is needed to provide the feedback and phase shift required for the oscillator. No other external components are required. If preferred, a resonator can also be connected between OSCI and OSCO for oscillation to occur, but two external capacitors connected between OSCI, OSCO and ground are required. The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if the system enters the power down mode, the system clock stops running, but the WDT oscillator still continues to run. The WDT oscillator can be disabled by a configuration option to conserve power. Watchdog Timer - WDT The WDT clock source is implemented by a dedicated RC oscillator (WDT oscillator) or the instruction clock Bit No. Label
0 1 2
WS0 WS1 WS2
Watchdog Timer division ratio selection bits Bit 2,1,0 = 000, Division Ratio = 1:1 Bit 2,1,0 = 001, Division Ratio = 1:2 Bit 2,1,0 = 010, Division Ratio = 1:4 Bit 2,1,0 = 011, Division Ratio = 1:8 Bit 2,1,0 = 100, Division Ratio = 1:16 Bit 2,1,0 = 101, Division Ratio = 1:32 Bit 2,1,0 = 110, Division Ratio = 1:64 Bit 2,1,0 = 111, Division Ratio = 1:128 Unused bit, read as 0
3 7~4 T3~T0
Test mode setting bits (T3,T2,T1,T0) = (0,1,0,1), enter DAC write mode. Otherwise normal operation. WDTS (09H) Register
W D T P r e s c a le r 8 - b it C o u n te r 7 - b it C o u n te r
W DT OSC S y s te m C lo c k /4
M ask O p tio n S e le c t
W S0~W S2
8 -to -1 M U X W D T T im e - o u t
Watchdog Timer
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CLR WDT and the other set CLR WDT1 and CLR WDT2. Of these two types of instruction, only one type of instruction can be active at a time depending on the configuration option CLR WDT times selection option. If the CLR WDT is selected (i.e., CLR WDT times equal one), any execution of the CLR WDT instruction clears the WDT. In the case that CLR WDT1 and CLR WDT2 are chosen (i.e., CLR WDT times equal two), these two instructions have to be executed to clear the WDT; otherwise, the WDT may reset the chip due to a time-out. Power Down Operation - HALT The HALT mode is initialized by the HALT instruction and results in the following:
* The system oscillator will be turned off but the WDT
wake-up. If the wake-up results from an interrupt acknowledge signal, the actual interrupt subroutine execution will be delayed by one or more cycles. If the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is finished. To minimize power consumption, all the I/O pins should be carefully managed before entering the HALT status. Reset There are four ways in which a reset can occur:
* RES reset during normal operation * RES reset during HALT * WDT time-out reset during normal operation * USB reset
oscillator remains running (if the WDT oscillator is selected).
* The contents of the on-chip RAM and registers remain
unchanged.
* The WDT and WDT prescaler will be cleared and re-
counted again (if the WDT clock is from the WDT oscillator).
* All of the I/O ports remain in their original status. * The PDF flag is set and the TO flag is cleared.
The WDT time-out during HALT is different from other chip reset conditions, since it can perform a warm reset that resets only the program counter and stack pointer, leaving the other circuits in their original state. Some registers remain unchanged during other reset conditions. Most registers are reset to the initial condition when the reset conditions are met. By examining the PDF and TO flags, the program can distinguish between different chip resets. TO 0 u 0 1 1 PDF 0 u 1 u 1 RESET Conditions RESET reset during power-up RESET reset during normal operation RESET wake-up HALT WDT time-out during normal operation WDT wake-up HALT
The system can leave the HALT mode by means of an external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset causes a device initialization and the WDT overflow performs a warm reset. After the TO and PDF flags are examined, the cause for chip reset can be determined. The PDF flag is cleared by a system power-up or executing the CLR WDT instruction and is set when executing the HALT instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the program counter and stack pointer; the others remain in their original status. The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit in port A can be independently selected to wake-up the device by configuration option. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If it awakens from an interrupt, two sequence may occur. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. If the interrupt is enabled and the stack is not full, the regular interrupt response takes place. If an interrupt request flag is set to 1 before entering the HALT mode, the wake-up function of the related interrupt will be disabled. Once a wake-up event occurs, it takes 1024 tSYS (system clock period) to resume normal operation. In other words, a dummy period will be inserted after a
Note: u stands for unchanged To guarantee that the system oscillator is started and stabilized, the SST (System Start-up Timer) provides an extra delay of 1024 system clock pulses when the system resets (power-up, WDT time-out or RES reset) or the system awakes from the HALT state. When a system reset occurs, the SST delay is added during the reset period. Any wake-up from HALT will enable the SST delay. The functional unit chip reset status are shown below. Program Counter Interrupt WDT 000H Disable Clear. After master reset, WDT begins counting
Timer/event Counter Off Input/output Ports Stack Pointer Input mode Points to the top of the stack
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V
DD
HALT W DT
W a rm
R eset
100kW 10kW 0 .1 m F
0 .0 1 m F RESET
RESET
OSCI
SST 1 0 - b it R ip p le C o u n te r S y s te m R eset
C o ld R eset
Reset Circuit
VDD RES S S T T im e - o u t C h ip R eset tS
ST
Reset Configuration
Reset Timing Chart The registers status are summarized in the following table. Reset (Power On) xxxx xxxx xxxx xxxx xxxx xxxx 000H xxxx xxxx -xxx xxxx 0000 0111 --00 xxxx -000 0000 xxxx xxxx xxxx xxxx 00-0 1000 xxxx xxxx xxxx xxxx 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 -000 0000 xxxx xxxx WDT RES Reset Time-out RES Reset (Normal (Normal (HALT) Operation) Operation) uuuu uuuu uuuu uuuu uuuu uuuu 000H uuuu uuuu -uuu uuuu 0000 0111 --1u uuuu -000 0000 uuuu uuuu uuuu uuuu 00-0 1000 uuuu uuuu uuuu uuuu 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 -000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 000H uuuu uuuu -uuu uuuu 0000 0111 --uu uuuu -000 0000 uuuu uuuu uuuu uuuu 00-0 1000 uuuu uuuu uuuu uuuu 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 -000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 000H uuuu uuuu -uuu uuuu 0000 0111 --01 uuuu -000 0000 uuuu uuuu uuuu uuuu 00-0 1000 uuuu uuuu uuuu uuuu 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 -000 0000 uuuu uuuu WDT Time-Out (HALT)* uuuu uuuu uuuu uuuu uuuu uuuu 000H uuuu uuuu -uuu uuuu uuuu uuuu --11 uuuu -uuu uuuu uuuu uuuu uuuu uuuu uu-u uuuu uuuu uuuu uuuu uuuu uu-u u--uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu USB Reset USB Reset (Normal) (HALT) uuuu uuuu uuuu uuuu uuuu uuuu 000H uuuu uuuu -uuu uuuu 0000 0111 --uu uuuu -000 0000 uuuu uuuu uuuu uuuu 00-0 1000 uuuu uuuu uuuu uuuu 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 -000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 000H uuuu uuuu -uuu uuuu 0000 0111 --01 uuuu -000 0000 uuuu uuuu uuuu uuuu 00-0 1000 uuuu uuuu uuuu uuuu 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 -000 0000 uuuu uuuu
Register
MP0 MP1 ACC Program Counter TBLP TBLH WDTS STATUS INTC0 TMR0H TMR0L TMR0C TMR1H TMR1L TMR1C PA PAC PB PBC PC PCC USVC INTC1 TBHP
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Reset (Power On) 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 xxxx x010 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0110 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 WDT RES Reset Time-out RES Reset (Normal (Normal (HALT) Operation) Operation) uuxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu xxxx x010 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0110 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 10xx 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 xxxx x010 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0110 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 10xx 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 xxxx x010 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0110 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 WDT Time-Out (HALT)* 10xx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu xxxx x010 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 0000 0000 0000 0uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu USB Reset USB Reset (Normal) (HALT) 1000 0u00 00uu 0000 0u00 u000 0000 0000 0000 0000 0u00 u000 0000 0000 xxxx x010 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 00uu uuuu 0uuu 0000 0uuu 0000 0000 0uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 1000 0u00 00uu 0000 0u00 u000 0000 0000 0000 0000 0u00 u000 0000 0000 xxxx x010 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 00uu uuuu 0uuu 0000 0uuu 0000 0000 0uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
Register
USC USR UCC AWR STALL SIES MISC SETIO FIFO0 FIFO1 FIFO2 FIFO3 FIFO4 DAC_LIMIT_L DAC_LIMIT_H DAC_WR PGA_CTRL PFDC PFDD MODE_CTRL SBCR SBDR PLAY_DATAL_L PLAY_DATAL_H PLAY_DATAR_L PLAY_DATAR_H RECORD_DATA_L RECORD_DATA_H
Note: * stands for warm reset u stands for unchanged x stands for unknown - stands for undefined
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Timer/Event Counter Two timer/event counters (TMR0, TMR1) are implemented in the microcontroller. The Timer/Event Counter 0/1 contains a 16-bit programmable count-up counter and the clock may come from an external source or an internal clock source. An internal clock source comes from fSYS/4. The external clock input allows the user to count external events, measure time intervals or pulse widths, or to generate an accurate time base. There are six registers related to the Timer/Event Counter 0; TMR0H (0CH), TMR0L (0DH), TMR0C (0EH) and the Timer/Event Counter 1; TMR1H (0FH), TMR1L (10H), TMR1C (11H). For 16-bit timer to write data to TMR0/1L will only put the written data to an internal lower-order byte buffer (8-bit) and writing TMR0/1H will transfer the specified data and the contents of the lower-order byte buffer to TMR0/1H and TMR0/1L registers. The Timer/Event Counter 0/1 preload register is changed by each writing TMR0/1H operations. Reading TMR0/1H will latch the contents of TMR0/1H and TMR0/1L counters to the destination and the lower-order byte buffer, respectively. Reading the TMR0/1L will read the contents of the lower-order byte buffer. The TMR0C (TMR1C) is the Timer/Event Counter 0 (1) control register, which defines the operating mode, counting enable or disable and an active edge. The TM0 and TM1 bits define the operation mode. The event count mode is used to count external events, which means that the clock source is from an external (TMR0, TMR1) pin. The timer mode functions as a normal timer with the clock source coming from the internal clock source. Finally, the pulse width measurement mode can be used to count the high level or low level duration of the external signal (TMR0, TMR1), and the counting is based on the internal clock source. In the event count or timer mode, the timer/event counter starts counting at the current contents in the timer/event counter and ends at FFFFH. Once an overflow occurs, the counter is reloaded from the timer/event counter preload register, and generates an interrupt request flag (T0F; bit 5 of INTC0, T1F; bit 6 of INTC0). In the pulse width measurement mode with the values of the TON and TE bits equal to 1, after the TMR0 (TMR1) has received a transient from low to high (or high to low if the TE bit is 0), it will start counting until the TMR0 (TMR1) returns to the original level and resets TON. The measured result remains in the timer/event counter even if the activated transient occurs again. In other words, only 1-cycle measurement can be made until TON is set. The cycle measurement will re-function as long as it receives further transient pulse. In this operation mode, the timer/event counter begins counting not according to the logic level but to the transient edges. In the case of counter overflows, the counter is reloaded from the timer/event counter register and issues an interrupt request, as in the other two modes, i.e., event and timer modes. To enable the counting operation, the Timer ON bit (TON; bit 4 of TMR0C or TMR1C) should be set to 1. In the pulse width measurement mode, TON is automatically cleared after the measurement cycle is completed. But in the other two modes, TON can only be reset by instructions. The overflow of the Timer/Event Counter 0/1 is one of the wake-up sources. No matter what the operation mode is, writing a 0 to ET0I or ET1I disables the related interrupt service. In the case of timer/event counter off condition, writing data to the timer/event counter preload register also reloads that data to the timer/event counter. But if the timer/event counter is turn on, data written to the timer/event counter is kept only in the timer/event counter preload register. The timer/event counter still continues its operation until an overflow occurs. When the timer/event counter (reading TMR0/TMR1) is read, the clock is blocked to avoid errors, as this may results in a counting error. Blocking of the clock should be taken into account by the programmer.
fS
Y S /4
f IN
T
D a ta B u s TM 1 TM 0 TE 1 6 B its T im e r /E v e n t C o u n te r P r e lo a d R e g is te r R e lo a d
T M R 0 /1
TM 1 TM 0 TON
P u ls e W id th M e a s u re m e n t M o d e C o n tro l
1 6 B its T im e r /E v e n t C o u n te r (T M R 0 /1 )
O v e r flo w to In te rru p t
Timer/Event Counter 0/1
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Bit No. 0~2, 5 Label 3/4 Unused bit, read as 0 Defines the TMR active edge of the timer/event counter: In Event Counter Mode (TM1,TM0)=(0,1): 1=count on falling edge; 0=count on rising edge In Pulse Width measurement mode (TM1,TM0)=(1,1): 1=start counting on the rising edge, stop on the falling edge; 0=start counting on the falling edge, stop on the rising edge Enable/disable the timer counting (0=disable; 1=enable) Defines the operating mode 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMR0C (0EH), TMR1C (11H) Register Input/Output Ports There are 24 bidirectional input/output lines in the micro-controller, labeled from PA to PC, which are mapped to the data memory of [12H], [14H], [16H] respectively. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction MOV A,[m] (m=12H, 14H, 16H). For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Each I/O line has its own control register (PAC, PBC, PCC) to control the input/output configuration. With this control register, CMOS output or Schmitt trigger input with or without pull-high resistor structures can be reconfigured dynamically (i.e. on-the-fly) under software control. To function as an input, the corresponding latch of the control register must write 1. The input source also depends on the control register. If the control register bit is 1 the input will read the pad state. If the control register bit is 0 the contents of the latches will move to the internal bus. The latter is possible in the Read-modify-write instruction. For output function, CMOS configurations can be selected. These control registers are mapped to locations 13H, 15H, 17H. After a chip reset, these input/output lines remain at high levels or floating state (depending on the pull-high
P u ll- H ig h O p tio n V
DD
Function
3
TE
4
TON
6 7
TM0 TM1
C o n tr o l B it
D a ta B u s W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r
D CK S
Q Q
D a ta B it Q D CK S Q
W r ite D a ta R e g is te r
PA0 PB0 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7
~PA ~PB /B Z /T M /T M /S /S /S /S DO DI CS CK
7 7
R0 R1
M R e a d D a ta R e g is te r S y s te m W a k e - u p ( P A o n ly ) B Z fo r P T M R 0 fo r P T M R 1 fo r P P S D O fo r P S D I fo r P S C S fo r P S C K fo r P C0 C1 C2 U
X C o n fig u r a tio n O p tio n
C3 C4 C5 C6 C7
Input/Output Ports
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options). Each bit of these input/output latches can be set or cleared by SET [m].i and CLR [m].i (m=12H, 14H, 16H ) instructions. Some instructions first input data and then follow the output operations. For example, SET [m].i, CLR [m].i, CPL [m], CPLA [m] read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. Each line of port A has the capability of waking-up the device. Low Voltage Reset - LVR (by Configuration Option) The LVR option is 3.0V. The microcontroller provides a low voltage reset circuit in order to monitor the supply voltage of the device. If the supply voltage of the device is within the range 0.9V~VLVR, the LVR will automatically reset the device internally. The LVR includes the following specifications:
* The low voltage (0.9V~VLVR) condition has to remain
(bit4 of the UCC). Since the Resume signal will be cleared before the Idle signal is sent out by the host and the Suspend line (bit 0 of USC) will go to 0. So when the MCU is detecting the Suspend line (bit0 of USC), the condition of the Resume line should be noted and taken into consideration. The following is the timing diagram:
SUSPEND U S B R e s u m e S ig n a l
U S B _ IN T
The device with remote wake up function can wake-up the USB Host by sending a wake-up pulse through RMWK (bit 1 of USC). Once the USB Host receives the wake-up signal from the HT82A832R, it will send a Resume signal to the device. The timing is as follows:
SUSPEND M in . 1 USB CLK
M in . 2 .5 m s U S B R e s u m e S ig n a l
in its condition for a time exceeding 1ms. If the low voltage state does not exceed 1ms, the LVR will ignore it and will not perform a reset function.
* The LVR uses the OR function with the external
RMW K
RESET signal to perform a chip reset. Suspend Wake-Up and Remote Wake-Up If there is no signal on the USB bus for over 3ms, the HT82A832R will go into a suspend mode. The Suspend line (bit 0 of the USC) will be set to 1 and a USB interrupt is triggered to indicate that the HT82A832R should jump to the suspend state to meet the requirements of the USB suspend current spec. In order to meet the requirements of the suspend current, the firmware should disable the USB clock by clearing USBCKEN (bit3 of UCC) to 0. Also the user can further decrease the suspend current by setting SUSP2 (bit4 of the UCC). When the resume signal is sent out by the host, the HT82A832R will be woken up by the USB interrupt and the Resume line (bit 3 of USC) will be set. In order to make the HT82A832R work properly, the firmware must set USBCKEN (bit 3 of UCC) to 1 and clear SUSP2
U S B _ IN T
USB Interface The HT82A832R device has 5 Endpoints (EP0~EP4). EP0 supports Control transfer. EP1 and EP4 support Interrupt transfer. EP2 supports Isochronous out transfer. EP3 supports Isochronous in transfer. These registers, including USC (20H), USR (21H), UCC (22H), AWR (23H), STALL (24H), SIES (25H), MISC (26H), FIFO0 (28H), FIFO1 (29H), FIFO2 (2AH), FIFO3 (2BH), FIFO4 (2CH) are used for the USB function. The FIFO size of each FIFO is 8 bytes (FIFO0), 8 bytes (FIFO1), 384 bytes (FIFO2), 32 bytes (FIFO3), 32 bytes (FIFO4). The total is 464 bytes. URD (bit7 of USC) is the USB reset signal control function definition bit.
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Bit No. Label R/W Reset Functions Read only, USB suspend indication. When this bit is set to 1 (set by SIE), it indicates that the USB bus has entered the suspend mode. The USB interrupt is also triggered when this bit changes from low to high. USB remote wake-up command. It is set by MCU to force the USB host to leave the suspend mode. USB reset indication. This bit is set/cleared by the USB SIE. This bit is used to detect a USB reset event on the USB bus. When this bit is set to 1, this indicates that a USB reset has occurred and that a USB interrupt will be initialized. USB resume indication. When the USB leaves the suspend mode, this bit is set to 1 (set by SIE). When the RESUME is set by SIE, an interrupt will be generated to wake-up the MCU. In order to detect the suspend state, the MCU should set USBCKEN and clear SUSP2 (in the UCC register) to enable the SIE detect function. RESUME will be cleared when the SUSP goes to 0. When the MCU is detecting the SUSP, the condition of RESUME (causes the MCU to wake-up) should be noted and taken into consideration. 0/1: Turn-off/on V33O output Undefined bit, read as 0. USB reset signal control function definition 1: USB reset signal will reset MCU 0: USB reset signal cannot reset MCU USC (20H) Register The USR (USB endpoint interrupt status register) register is used to indicate which endpoint is accessed and to select the serial bus (USB). The endpoint request flags (EP0F, EP1F, EP2F, EP3F, EP4F) are used to indicate which endpoints are accessed. If an endpoint is accessed, the related endpoint request flag will be set to 1 and the USB interrupt will occur (if the USB interrupt is enabled and the stack is not full). When the active endpoint request flag is serviced, the endpoint request flag has to be cleared to 0 by software. Bit No. 0 Label EP0F R/W R/W Reset 0 Functions When this bit is set to 1 (set by SIE), it indicates that endpoint 0 has been accessed and a USB interrupt will occur. When the interrupt has been serviced, this bit should be cleared by software. When this bit is set to 1 (set by SIE), it indicates that endpoint 1 has been accessed and a USB interrupt will occur. When the interrupt has been serviced, this bit should be cleared by software. When this bit is set to 1 (set by SIE), it indicates that endpoint 2 has been accessed and a USB interrupt will occur. When the interrupt has been serviced, this bit should be cleared by software. When this bit is set to 1 (set by SIE), it indicates that endpoint 3 has been accessed and a USB interrupt will occur. When the interrupt has been serviced, this bit should be cleared by software. When this bit is set to 1 (set by SIE), it indicates that endpoint 4 has been accessed and a USB interrupt will occur. When the interrupt has been serviced, this bit should be cleared by software. Undefined bit, read as 0. USR (21H) Register
0
SUSP
R
0
1
RMWK
R/W
0
2
URST
R/W
0
3
RESUME
R
0
4 5~6 7
V33C 3/4 URD
R/W 3/4 R/W
0 3/4 1
1
EP1F
R/W
0
2
EP2F
R/W
0
3
EP3F
R/W
0
4 5~7
EP4F 3/4
R/W 3/4
0 3/4
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There is a system clock control register implemented to select the clock used in the MCU. This register consists of a USB clock control bit (USBCKEN), a second suspend mode control bit (SUSP2) and a system clock selection bit (SYSCLK). The endpoint selection is determined by EPS2, EPS1 and EPS0. Bit No. Label R/W Reset Functions Accessing endpoint FIFO selection, EPS2, EPS1, EPS0: 000: Select endpoint 0 FIFO 001: Select endpoint 1 FIFO 010: Select endpoint 2 FIFO 011: Select endpoint 3 FIFO 100: Select endpoint 4 FIFO 101: reserved for future expansion, cannot be used 110: reserved for future expansion, cannot be used 111: reserved for future expansion, cannot be used If the selected endpoints do not exist, the related function will be absent. USB clock control bit. When this bit is set to 1, it indicates that the USB clock is enabled. Otherwise, the USB clock is turned-off. This bit is used for reducing power consumption in the suspend mode. In normal mode, clear this bit to 0 In the HALT mode, set this bit to 1 to reducing power consumption. This bit is used to define if the MCU system clock comes form an external OSC or comes from the PLL output 24MHz clock. 0: system clock sourced from OSC 1: system clock sourced from the PLL output 24MHz This bit is used to specify the MCU system clock oscillator frequency. For a 6MHz crystal oscillator or resonator, set this bit to 1. For a 12MHz crystal oscillator or resonator, clear this bit to 0.
0~2
EPS0~ EPS2
R/W
0
3
USBCKEN
R/W
0
4
SUSP2
R/W
0
5
fSYS24MHz
R/W
0
6
SYSCLK
R/W
0
Note: Isochronous endpoint 2 and endpoint 3 are implemented by hardware, so FIFO2 and FIFO3 cannot read/write via firmware. UCC (22H) Register The AWR register contains the current address and a remote wake up function control bit. The initial value of AWR is 00H. The address value extracted from the the USB command has not to be loaded into this register until the SETUP stage has finished. Bit No. 0 1~7 Label WKEN AD0~AD6 R/W R/W R/W Power-on 0 0000000 Functions USB remote-wake-up enable/disable (1/0) USB device address
AWR (23H) Register The STALL register shows if the corresponding endpoint works properly or not. As soon as the endpoint works improperly, the related bit in the STALL has to be set to 1. The STALL register will be cleared by a USB reset signal. Bit No. 0~4 5~7 Label STL0~STL4 STL5~STL7 R/W R/W 3/4 Power-on 00000 000 Functions Set by the user when related USB endpoints were stalled. Cleared by a USB reset and a Setup Token event. Undefined bit, read as 0.
STALL (24H) Register
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Bit No. Label R/W Power-on Functions This bit is used to configure the SIE to automatically change the device address by the value stored in the AWR register. When this bit is set to 1 by firmware, the SIE will update the device address by the value stored in the AWR register after the PC host has successfully read the data from the device by an IN operation. Otherwise, when this bit is cleared to 0, the SIE will update the device address immediately after an address is written to the AWR register. So, in order to work properly, the firmware has to clear this bit after a next valid SETUP token is received. This bit is used to indicate that some errors have occurred when the FIFO0 is accessed. This bit is set by SIE and should be cleared by firmware. This bit is used to indicate the OUT token (except the OUT zero length token) has been received. The firmware clears this bit after the OUT data has been read. Also, this bit will be cleared by SIE after the next valid SETUP token is received. This bit is used to indicate the current USB receiving signal from PC host is an IN token. This bit is used to indicate the SIE is a transmitted NAK signal to the host in response to the PC host IN or OUT token. Error condition failure flag include CRC, PID, no integrate token error, CRCF will be set by hardware and the CRCF need to be cleared by firmware. Token pakcage active flag, low active. NAK token interrupt mask flag. If this bit set, when the device sent a NAK token to the host, an interrupt will be disabled. Otherwise if this bit is cleared, when the device sends a NAK token to the host, it will enter the interrupt sub-routine. SIES (25H) Register The MISC register combines command and status to control the desired endpoint FIFO action and to show the status of the desired endpoint FIFO. MISC will be cleared by a USB reset signal. Bit No. 0 Label REQUEST R/W R/W Power-on 0 Functions After setting the status of the desired one, FIFO can be requested by setting this bit high . After finishing, this bit must be set low. To represent the direction and transition end MCU access. When set to logic 1, the MCU desires to write data to the FIFO. After finishing, this bit must be set to logic 0 before terminating request to represent transition end. For an MCU read operation, this bit must be set to logic 0 and set to logic 1 after finishing. MCU requests to clear the FIFO, even if the FIFO is not ready. After clearing the FIFO, the USB interface will send force_tx_err to tell the Host that data under-run if the Host wants to read data. Enables the isochronous in pipe interrupt. Enables the isochronous out pipe interrupt. To show that the data in the FIFO is a setup command. This bit will remain in this state until the next one enters the FIFO. To show that the desired FIFO is ready To show that the host sent a 0-sized packet to the MCU. This bit must be cleared by a read action to the corresponding FIFO. MISC (26H) Register
0
ASET
R/W
0
1
ERR
R/W
0
2
OUT
R/W
0
3 4 5 6
IN NAK CRCF EOT
R R R/W R
0 0 0 1
7
NMI
R/W
0
1
TX
R/W
0
2 3 4 5 6 7
CLEAR ISO_IN_EN ISO_OUT_EN SETCMD READY LEN0
R/W R/W R/W R/W R R
0 0 0 0 0 0
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Bit No. 0 1 2 3 4 5~7 Label DATATG* SETIO1** SETIO2** SETIO3** SETIO4** 3/4 R/W R/W R/W R/W R/W R/W 3/4 Power-on 0 1 0 1 1 3/4 DATA token toggle bit Set endpoint1 input or output pipe (1/0), default input pipe(1) Set endpoint2 input or output pipe (1/0), default output pipe(0) Set endpoint3 input or output pipe (1/0), default input pipe(1) Set endpoint4 input or output pipe (1/0), default input pipe(1) Undefined bit, read as 0 Functions
Note: *USB definition: when the host sends a set Configuration, the Data pipe should send the DATA0 (about the Data toggle) first. So, when the Device receives a set configuration setup command, the user needs to toggle this bit as the following data will send a Data0 first. **It is only required to set the data pipe as an input pile or output pile. The purpose of this function is to avoid the host sending a abnormal IN or OUT token and disabling the endpoint. SETIO (27H) Register, USB Endpoint 1 ~ Endpoint 4 Set IN/OUT Pipe Register The speaker output volume and speaker mute/un-mute are controlled by the USB Speaker Volume Control register. The range of the volume is set from 6 dB to -32 dB by software. Speaker mute control: MUTEB=0: Mute Speaker output MUTEB=1: Normal Bit No. 0~6 7 Label USVC0~ USVC6 MUTE R/W R/W R/W Power-on 0 0 Volume control Bit0~Bit6 Mute control, low active. Functions
USB Speaker Volume Control (1CH) Register Result (dB) 6 5.5 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 -0.5 -1 -1.5 USVC 000_1100 000_1011 000_1010 000_1001 000_1000 000_0111 000_0110 000_0101 000_0100 000_0011 000_0010 000_0001 000_0000 111_1111 111_1110 111_1101 Result (dB) -2 -2.5 -3 -3.5 -4 -4.5 -5 -5.5 -6 -6.5 -7 -7.5 -8 -8.5 -9 -9.5 USVC 111_1100 111_1011 111_1010 111_1001 111_1000 111_0111 111_0110 111_0101 111_0100 111_0011 111_0010 111_0001 111_0000 110_1111 110_1110 110_1101 Result (dB) -10 -10.5 -11 -11.5 -12 -13 -14 -15 -16 -17 -18 -19 -20 -21 -22 -23 USVC 110_1100 110_1011 110_1010 110_1001 110_1000 110_0111 110_0110 110_0101 110_0100 110_0011 110_0010 110_0001 110_0000 101_1111 101_1110 101_1101 Result (dB) -24 -25 -26 -27 -28 -29 -30 -31 -32 USVC 101_1100 101_1011 101_1010 101_1001 101_1000 101_0111 101_0110 101_0101 101_0100
Speaker Volume Control Table
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Label FIFO0~ FIFO4 R/W R/W Power-on xxH Functions EPi accessing register (i = 0~4). When an endpoint is disabled, the corresponding accessing register should be disabled.
FIFO0~4 (28H~2CH) USB Endpoint Accessing Register Definitions DAC_Limit_L and DAC_Limit_H are used to define the 16-bit DAC output limit. DAC_Limit_L and DAC_Limit_H are unsigned value. If the 16-bit data from the Host over the range defined by DAC_Limit_L and DAC_Limit_H, the output digital code to DAC will be clamped. DAC_Limit_L DAC_Limit_H Example to set the DAC output limit value: ;----------------------------------------------------------; Set DAC Limit Value=FF00H ;----------------------------------------------------------clr [02DH] ; Set DAC Limit low byte=00H set [02EH] ; Set DAC Limit high byte=FFH ;----------------------------------------------------------In order to prevent a popping noise from the speaker output, the power amplifier should output a value of VDD/2 (send 8000H to DAC) during the initial power on state. If the software is set high then clear the bit DAC_WR_TRIG (bit 3 of DAC_WR register), the value on the DAC_Limit_L and DAC_Limit_H registers will write to the DAC. Bit No. 0~2, 4~7 3 Label 3/4 DAC_WR_TRIG R/W R R/W Power-on 0 0 Functions Undefined bit, read as 0. DAC write trigger bit DAC output limit low byte DAC output limit high byte
DAC_WR (2FH) Register Example to avoid popping noise: System_Initial: ;----------------------------------------------------------; Avoid Pop Noise ;----------------------------------------------------------mov a,WDTS mov FIFO_TEMP,a ;Save WDTS value mov a,00001111b andm a,WDTS mov a,01010000b orm a,WDTS ;Enter DAC Write Data mode, high nibble of WDTS=0101b clr [02DH] ;Set DAC data low byte=00H mov a,80H mov [02EH],a ;Set DAC data high byte=80H nop ;Write 8000H to DAC set [02FH].3 nop clr [02FH].3 nop ;----------------------------------------------------------mov a,FIFO_TEMP ;Restore WDTS value mov WDTS,a ;Quit DAC Write Data mode ;----------------------------------------------------------Note: At DAC write data mode (high nibble of WDTS register is 0101b), DAC_Limit_L and DAC_Limit_H registers will be the 16-bit DAC input data register at falling edge of DAC_WR_TRIG. Otherwise, these two registers are used to define the 16-bit DAC output limit.
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Digital PGA Bit No. 0~5 6 7 Label Functions
There are six bits to control the digital PGA (0~19.5 dB). The PGA is a digital amplifier PGA0~PGA5 used to amplify the 16-bit data that comes from the PCM ADC. The PGA value versus gain relationship is shown in the follow table. 3/4 MUTE_MKB Undefined bit, read as 0. Microphone mute Control: MUTE_MKB =0: Mute microphone input. MUTE_MKB =1: Normal. PGA_CTRL (30H) Register PGA_CRTL Value (PGA5~PGA0) Gain (dB) 0 0.5 : : 19.5 19.5 : : 19.5
000000 000001 : : 100111 101000 : : 111111 PFD Control Label PFDC PFDD Bit 7 0 PFDD7 Bit 6 PRES1 PFDD6 Bit 5 PRES0 PFDD5
Bit 4 PFDEN PFDD4
Bit 3 0 PFDD3
Bit 2 0 PFDD2
Bit 1 PFD_IO PFDD1
Bit 0 SELW PFDD0
The PFD (programmable frequency divider) is implemented in the HT82A832R. It is composed of two portions: a prescaler and a general counter. The prescaler is controlled by the register bits, PRES0 and PRES1. The 4-stage prescaler is divided by 16. The general counter is programmed by an 8-bit register PFDD. The PFDD is inhibited to write while the PFD is disabled. To modify the PFDD contents, the PFD must be enabled. When the generator is disabled, the PFDD is cleared by hardware. PFD prescaler selection: PRES1 0 0 1 1 PRES0 0 1 0 1 PFD frequency source 1 PFD frequency source 2 PFD frequency source 4 PFD frequency source 8 Prescaler Output
The bit PFD_IO is used to determine whether PC0 is a general purpose I/O port or a PFD output. Label PFD_IO=1 PFD_IO=0 PC0 is PFD output PC0 is a general purpose IO Port (Default =0) Functions
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The SELW bit is used to control the power amplifier input source. The software should set SELW= 1 when the power amplifier signal come from MUSIC_IN, otherwise the speaker output will come from USB Audio data. Label SELW=1 SELW=0 Functions Power amplifier signal is sourced from MUSIC_IN pin Power amplifier signal is sourced from USB Audio data (default =0)
PFD F re q u e n c y P r e s c a le r O u tp u t PFD O u tp u t
fS
YS
/4
4 - S ta g e P r e s c a le r (1 /1 6 )
P r e s c a le r
PFDD
PR ES1,PR ES0 N o te : P F D O u tp u t F re q u e n c y = P r e s c a le r O u tp u t 2 (N + 1 )
PFDEN
, w h e r e N = th e v a lu e o f th e P F D
d a ta
SPI The serial interface function similar to SPI (Motorola), where four basic signals are included. They are SDI (Serial Data Input), SDO (Serial Data Output), SCK (serial clock) and SCS (slave select pin).
SCS
SCK
SDI
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
SDO
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
SPI Timing Label SBCR Default SBDR Default Functions Serial Bus Control Register Serial Bus Data Register D7 CKS 0 D7 U D6 M1 1 D6 U D5 M0 1 D5 U D4 SBEN 0 D4 U D3 MLS 0 D3 U D2 CSEN 0 D2 U D1 WCOL 0 D1 U D0 TRF 0 D0 U
Note: U unchanged Two registers (SBCR & SBDR) unique to the serial interface provide control, status and data storage.
* SBCR: Serial bus control register

Bit7 (CKS): clock source selection: fSIO=fSYS/2, select as 0; fSIO=fSYS, select as 1 Bit6 (M1), Bit5 (M0): master/slave mode and baud rate selection
-
M1, M0= 00: Master mode, baud rate = fSIO 01: Master mode, baud rate = fSIO/4 10: Master mode, baud rate = fSIO/16 11: Slave mode Enable: (SCS dependent on CSEN bit) Disable (R) enable: SCK, SDI, SDO, SCS =0 (SCK=0) and wait to write data to SBDR (TXRX buffer) Master mode: write data to SBDR (TXRX buffer) (R) start transmission/reception automatically Master mode: when data has been transferred (R) set TRF Slave mode: when a SCK (and SCS dependent on CSEN) is received, data in TXRX buffer is shifted-out and data on SDI is shifted-in.
Bit4 (SBEN): Serial bus enable/disable (1/0)
-
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-
Disable: SCK (SCK), SDI, SDO, SCS floating and related pins are IO ports. Label SBEN=1 SBEN=0 Functions PC4~PC7 are SPI function pins (pin SCS will go low if CSEN=1). PC4~PC7 are general purpose I/O Port pins (Default)
Note: 1. If SBEN=1, the pull-high resistors on PC4~PC7 will be disabled. When this happens the user should add external pull-high resistors to the SPI related pins if necessary (EX: pin SCS). 2. If CSEN=0, the SCS pin will enter a floating state.

Bit3 (MLS): MSB or LSB (1/0) shift first control bit Bit2 (CSEN): serial bus selection signal enable/disable (SCS), when CSEN=0, SCS is floating Bit1 (WCOL): this bit is set to 1 if data is written to SBDR (TXRX buffer) when a data is transferring (R) writing will be ignored if data is written to SBDR (TXRX buffer) when a data is transferring WCOL will be set by hardware and clear by software. Bit 0 (TRF): data transferred or data received (R) used to generate interrupt Note: data receiving is still working when MCU enters halt mode
* SBDR: Serial bus data register
Data written to SBDR (R) write data to TXRX buffer only Data read from SBDR (R) read from SBDR only
Operating Mode description: Master transmitter: clock sending and data I/O started by writing SBDR Master clock sending started by writing SBDR Slave transmitter: data I/O started by clock received Slave receiver: data I/O started by clock received
* Clock polarity = rising (CLK) or falling (CLK): 1 or 0 (software option)
Operation of Serial Interface: Label Functions
* Select CKS and select M1,M0 = 00, 01, 10 * Select CSEN, MLS (same as slave) * Set SBEN * Writing data to SBDR (R) data is stored in TXRX buffer (R) output CLK (and SCS) signals (R) go to
Master
* * * * *
step 5 (R) (SIO internal operation (R) data stored in TXRX buffer, and SDI data is shifted into TXRX buffer (R) data transferred, data in TXRX buffer is latched into SBDR) Check WCOL; WCOL = 1 (R) clear WCOL and go to step 4; WCOL = 0 (R) go to step 6 Check TRF or waiting for SBI (serial bus interrupt) Read data from SBDR Clear TRF Go to step 4
* CKS dont care and select M1, M0 = 11 * Select CSEN, MLS (same as master) * Set SBEN * Writing data to SBDR (R) data is store in TXRX buffer (R) waiting for master clock signal (and
Slave
* * * * *
SCS): CLK (R) go to step 5 (R) (SIO internal operations (R) CLK (SCS) received (R) output data in TXRX buffer and SDI data is shifted into TXRX buffer (R) data transferred, data in TXRX buffer is latched into SBDR) Check WCOL; WCOL = 1 (R) clear WCOL, go to step 4; WCOL = 0 (R) go to step 6 Check TRF or waiting for SBI (serial bus interrupt) Read data from SBDR Clear TRF Go to step 4
* WCOL: master/slave mode, set if writing to SBDR when data is transferring (transmitting or receiving) and this writing
will be ignored. WCOL function can be enabled/disabled by software option (SIO_WCOL bit of MODE_CTRL register). WCOL is set by SIO and cleared by users. Data transmission and reception are still workable when MCU enters halt mode. CPOL is used to select the clock polarity of CLK. It is a software option (SIO_CPOL bit of MODE_CTRL register).
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* MLS: MSB or LSB first selection * CSEN: chip select function enable/disable, CSEN = 1 (R) SCS signal function is active. Master should output SCS sig-
nal before CLK signal is setting and slave data transferring should be disabled(enabled) before(after) SCS signal received. CSEN = 0, SCS signal is not needed, SCS pin (master and slave) should be floating.
* CSEN: CSEN software option (SIO_CSEN bit of MODE_CTRL register) is used to enable/disable software CSEN
function. If CSEN software option is disable, software CSEN always disabled. If CSEN software option is enabled, software CSEN function can be used.
* SBEN = 1 (R) serial bus standby; SCS (CSEN = 1) = 1; SCS = floating (CSEN = 0); SDI = floating; SDO = 1; master
CLK = output 1/0 (dependent on CPOL software option), slave CLK = floating
* SBEN = 0 (R) serial bus disable; SCS = SDI = SDO = CLK = floating * TRF is set by SIO and cleared by users. When data transferring (transmission and reception) is complete, TRF is set
to generate SBI (serial bus interrupt).
S B E N = 1 , C S E N = 1 a n d w r ite d a ta to S B D R SCS ( if p u ll- h ig h e d )
CLK
SDI
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
SDO
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
CLK
SIO Timing Label SBCR Default SBDR Default Functions Serial Bus Control Register Serial Bus Data Register D7 CKS 0 D7 U D6 M1 1 D6 U D5 M0 1 D5 U D4 SBEN 0 D4 U D3 MLS 0 D3 U D2 CSEN 0 D2 U D1 WCOL 0 D1 U D0 TRF 0 D0 U
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D a ta B u s
SBDR
( R e c e iv e d D a ta R e g is te r )
D7
D6
D5
D4
D3
D2
D1
D0 M
U X
SDO
B u ffe r
SDO
M LS M In te rn a l B a u d R a te C lo c k EN SCK A n d , S ta rt C lo c k P o la r ity SBEN A n d , S ta rt EN M a s te r o r S la v e SBEN CSEN U X SDI
SBEN
A n d , S ta rt M
U X
C0
C1
C2 AND
TRF W C O L F la g
M a s te r o r S la v e
In te r n a l B u s y F la g SBEN SCS
W r ite S B D R W r ite S B D R E n a b le /D is a b le W r ite S B D R
Block Diagram of SIO Label WCOL CESN set by SIO cleared by users Enable or disable chip selection function pin Master mode: 1/0=with/without SCS output control Slave mode: 1/0= with/without SCS input control Enable or disable serial bus (0= initialize all status flags) When SBEN=0, all status flags should be initialized When SBEN=0, all SIO related function pins should stay at floating state 1= data transmitted or received 0= data is transmitting or still not received Functions
SBEN
TRF
If clock polarity set to rising edge (SIO_CPOL=1), serial clock timing follow CLK, otherwise (SIO_CPOL=0) CLK is the serial clock timing.
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Mode Control The MODE_CTRL register is used to control DAC and ADC operation mode and SPI function. Bit No. 0 Label DA_L_ENB Functions DAC enable/disable control (left channel) 1= DAC Left Channel disable 0= DAC Left Channel enable (default) DAC enable/disable control (right channel) 1= DAC Right Channel disable 0= DAC Right Channel enable (default) ADC enable/disable control 1= ADC power down 0= ADC power on (default) DAC play mode control 1= 8kHz/16-bit 0= 48kHz/16-bit (default) There are three bits used to control the mode of SPI operation. 1= clock polarity rising edge 0= clock polarity falling edge (default) 1= WCOL bit of SBCR register enable 0= WCOL bit of SBCR register disable (default) 1= CSEN bit of SBCR register enable 0= CSEN bit of SBCR register disable (Default) Undefined bit, read as 0 MODE_CTRL (34H) Register SPI Usage Example SPI_Test: clr UCC.@UCC_SYSCLK ;12MHz SYSCLK set SIO_CSEN ;SPI Chip Select Function Enable clr SIO_CPOL ;falling edge change data ;Master Mode, SCLK=fSIO clr M1 clr M0 ;-------------clr CKS ;fSIO=fsys/2 clr TRF ;clear TRF flag clr TRF_INT ;clear Interrupt SPI flag set MLS ;MSB shift first set CSEN ;Chip Select Enable set SBEN ;SPI Enable, SCS will go low if POLLING_MODE clr ESII ;SPI Interrupt Disable ;WRITE INTO "WRITE ENABLE" INSTRUCTION MOV A,OP_WREN MOV SBDR,A $0: snz TRF jmp $0 clr TRF else set ESII ;SPI Interrupt Enable ;WRITE INTO "WRITE ENABLE" INSTRUCTION MOV A,OP_WREN MOV SBDR,A $0: snz TRF_INT ;set at SPI Interrupt jmp $0 clr TRF_INT endif
1
DA_R_ENB
2
AD_ENB
3
PLAY_MODE
4
SIO_CPOL
5 6 7
SIO_WCOL SIO_CSEN 3/4
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Play/Record Data The play/record interrupt will be activated when play/record data is valid on PLAY_DATA/ RECORD_DATA registers. The PLAY_DATA/RECORD_DATA registers will latch data until next interrupt happen. The PLAY_DATA is unsigned value (0~FFFFH). RECORD_DATA is 2s complement value (8000H~7FFFH). The update rate of RECORD_DATA is 8KHz. The update rate of PLAY_DATA is 48KHz (PLAY_MODE=0) or 8KHz (PLAY_MODE=1). All these registers (3AH~3FH) are read only. Address 3AH 3BH 3CH 3DH 3EH 3FH Label PLAY_DATAL_L PLAY_DATAL_H PLAY_DATAR_L PLAY_DATAR_H RECORD_DATA_L RECORD_DATA_H Bit 7 PL_D7 Bit 6 PL_D6 Bit 5 PL_D5 Bit 4 PL_D4 Bit 3 PL_D3 Bit 2 PL_D2 Bit 1 PL_D1 PL_D9 PR_D1 PR_D9 R_D1 R_D9 Bit 0 PL_D0 PL_D8 PR_D0 PR_D8 R_D0 R_D8
PL_D15 PL_D14 PL_D13 PL_D12 PL_D11 PL_D10 PR_D7 PR_D6 PR_D5 PR_D4 PR_D3 PR_D2
PR_D15 PR_D14 PR_D13 PR_D12 PR_D11 PR_D10 R_D7 R_D15 R_D6 R_D14 R_D5 R_D13 R_D4 R_D12 R_D3 R_D11 R_D2 R_D10
Configuration Options The following table shows all of the configuration options in the microcontroller. All of the OTP options must be defined to ensure proper system functioning. No. 1 2 3 4 5 6 7 8 9 Option PA0~PA7 pull-high resistor enabled or disabled (by bit) LVR enable or disable WDT enable or disable WDT clock source: fSYS/4 or WDTOSC CLRWDT instruction(s): 1 or 2 PA0~PA7 wake-up enabled or disabled (by bit) PB0~PB7 pull-high resistor enabled or disabled (by bit) PC0~PC7 pull-high resistor enabled or disabled (by nibble) TBHP enable or disable (default disable)
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Application Circuits
USB CON VDD USB+ USBVSS 4 1 2 3 VSS 2 33W 33W 1 V VDD
DD
JP 5
0 .1 m F
V 1 .5 k W USBDN V33O USBDP
DD
2 SPILC D PC PC PC PC 7 6 5 4 SCS M IS O MOSI SCK 1 HEADER 2 1M W
PC0 M U S IC _ IN
50kW
100pF
Bead
47pF
47pF
0 .1 m F
10mF
47W V PC0 1kW
DD
100mF 100mF
LO UT ROUT AVSS2 V
DD
PA3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PA2 330W PA1 PA0 AVDD2 ROUT B e a d F e r r ite 1 2 LO UT AVSS2 AVSS1 B IA S M U S IC _ IN AVDD1 AVDD3 VAG R ef
PA3 PA2 PA1 PA0 AVDD2 ROUT LO UT AVSS2 AVSS1 B IA S M U S IC _ IN AVDD1 AVDD3 VAG R ef VAG T I+ T ITG AVSS3 PB7 PB6 PB5 PB4 DVSS2
PA4 PA5 PA6 PA7 DVSS1 V33O USBDP USBDN DVDD1 RESET OSCO OSCI P C 0 /B Z P C 1 /T M R 0 P C 2 /T M R 1 PC3 P C 4 /S D O P C 5 /S D I P C 6 /S C S P C 7 /S C K PB0 PB1 PB2 PB3
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
PA4 PA5 PA6 PA7 DVSS1 V33O USBDP USBDN DVDD RESET OSCO OSCI PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PB0 PB1 PB2 PB3 PA7 PA6 PA5 PA4 PB0 PB1 PB2 PB3 PB4 PB5 S11 S21 S31 S41 S51 S61 S21 S22 S32 S42 S52 S62 S13 S23 S33 S43 S53 S63
22pF
B uzzer
S peaker V
DD
0 .1 m F
1 2
B e a d F e r r ite
0 .1 m F
10mF
V
DD
10W
0 .1 m F 0 .1 m F
100kW Y1 12M Hz 1M W
0 .1 m F 22pF
DVDD
10mF
V
DD
B e a d F e r r ite 1 2
0 .1 m F
10mF
V
DD
1 2
AVSS3
1mF
VAG T I+ T ITG
0 .1 m F
10mF
AVDD3
1 AVSS3 VAG F e r r ite Bead
2
AVSS3 PB7 PB6 PB5 PB4 DVSS2
1kW 10mF
S14 S24 S34 S44 S54 S64
3 .3 k W
100kW 10kW 300pF
0 .1 m F
T I+
H T82A 832R
100kW
0 .1 m F
M ic r o p h o n e AVSS3
10kW
T I-
300pF
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Instruction Set Summary
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Add data memory to ACC Add ACC to data memory Add immediate data to ACC Add data memory to ACC with carry Add ACC to data memory with carry Subtract immediate data from ACC Subtract data memory from ACC Subtract data memory from ACC with result in data memory Subtract data memory from ACC with carry Subtract data memory from ACC with carry and result in data memory Decimal adjust ACC for addition with result in data memory 1 1(1) 1 1 1(1) 1 1 1(1) 1 1(1) 1(1) Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV C Description Instruction Cycle Flag Affected
Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC Complement data memory Complement data memory with result in ACC 1 1 1 1(1) 1(1) 1(1) 1 1 1 1(1) 1 Z Z Z Z Z Z Z Z Z Z Z
Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Clear bit of data memory Set bit of data memory 1(1) 1(1) None None Move data memory to ACC Move ACC to data memory Move immediate data to ACC 1 1(1) 1 None None None Rotate data memory right with result in ACC Rotate data memory right Rotate data memory right through carry with result in ACC Rotate data memory right through carry Rotate data memory left with result in ACC Rotate data memory left Rotate data memory left through carry with result in ACC Rotate data memory left through carry 1 1(1) 1 1(1) 1 1(1) 1 1(1) None None C C None None C C Increment data memory with result in ACC Increment data memory Decrement data memory with result in ACC Decrement data memory 1 1(1) 1 1(1) Z Z Z Z
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Mnemonic Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT No operation Clear data memory Set data memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of data memory Swap nibbles of data memory with result in ACC Enter power down mode 1 1(1) 1(1) 1 1 1 1(1) 1 1 None None None TO,PDF TO(4),PDF(4) TO(4),PDF(4) None None TO,PDF Read ROM code (current page) to data memory and TBLH Read ROM code (last page) to data memory and TBLH 2(1) 2(1) None None Jump unconditionally Skip if data memory is zero Skip if data memory is zero with data movement to ACC Skip if bit i of data memory is zero Skip if bit i of data memory is not zero Skip if increment data memory is zero Skip if decrement data memory is zero Skip if increment data memory is zero with result in ACC Skip if decrement data memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1(2) 1(2) 1(2) 1(2) 1(3) 1(3) 1(2) 1(2) 2 2 2 2 None None None None None None None None None None None None None Description Instruction Cycle Flag Affected
Note: x: Immediate data m: Data memory address A: Accumulator i: 0~7 number of bits addr: Program memory address O: Flag is affected -: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). : If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). Otherwise the original instruction cycle is unchanged. : and (2)
(2)
(3) (1) (4)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged.
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Instruction Definition
ADC A,[m] Description Operation Affected flag(s) TO 3/4 ADCM A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,x Description Operation Affected flag(s) TO 3/4 ADDM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Add data memory and carry to the accumulator The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator. ACC ACC+[m]+C
Add the accumulator and carry to data memory The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory. [m] ACC+[m]+C
Add data memory to the accumulator The contents of the specified data memory and the accumulator are added. The result is stored in the accumulator. ACC ACC+[m]
Add immediate data to the accumulator The contents of the accumulator and the specified data are added, leaving the result in the accumulator. ACC ACC+x
Add the accumulator to the data memory The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. [m] ACC+[m]
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AND A,[m] Description Operation Affected flag(s) TO 3/4 AND A,x Description Operation Affected flag(s) TO 3/4 ANDM A,[m] Description Operation Affected flag(s) TO 3/4 CALL addr Description PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical AND accumulator with data memory Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND [m]
Logical AND immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND x
Logical AND data memory with the accumulator Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory. [m] ACC AND [m]
Subroutine call The instruction unconditionally calls a subroutine located at the indicated address. The program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. The indicated address is then loaded. Program execution continues with the instruction at this address. Stack Program Counter+1 Program Counter addr TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation
Affected flag(s)
CLR [m] Description Operation Affected flag(s)
Clear data memory The contents of the specified data memory are cleared to 0. [m] 00H TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
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CLR [m].i Description Operation Affected flag(s) TO 3/4 CLR WDT Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Clear bit of data memory The bit i of the specified data memory is cleared to 0. [m].i 0
Clear Watchdog Timer The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are cleared. WDT 00H PDF and TO 0 TO 0 PDF 0 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
CLR WDT1 Description
Preclear Watchdog Timer Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0* TO 0* PDF 0* OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation
Affected flag(s)
CLR WDT2 Description
Preclear Watchdog Timer Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0* TO 0* PDF 0* OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation
Affected flag(s)
CPL [m] Description Operation Affected flag(s)
Complement data memory Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. [m] [m] TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4
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CPLA [m] Description Complement data memory and place result in the accumulator Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remain unchanged. ACC [m] TO 3/4 DAA [m] Description PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4
Operation Affected flag(s)
Decimal-Adjust accumulator for addition The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored in the data memory and only the carry flag (C) may be affected. If ACC.3~ACC.0 >9 or AC=1 then [m].3~[m].0 (ACC.3~ACC.0)+6, AC1=AC else [m].3~[m].0 (ACC.3~ACC.0), AC1=0 and If ACC.7~ACC.4+AC1 >9 or C=1 then [m].7~[m].4 ACC.7~ACC.4+6+AC1,C=1 else [m].7~[m].4 ACC.7~ACC.4+AC1,C=C TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
DEC [m] Description Operation Affected flag(s)
Decrement data memory Data in the specified data memory is decremented by 1. [m] [m]-1 TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4
DECA [m] Description Operation Affected flag(s)
Decrement data memory and place result in the accumulator Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]-1 TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4
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HALT Description Enter power down mode This instruction stops program execution and turns off the system clock. The contents of the RAM and registers are retained. The WDT and prescaler are cleared. The power down bit (PDF) is set and the WDT time-out bit (TO) is cleared. Program Counter Program Counter+1 PDF 1 TO 0 TO 0 INC [m] Description Operation Affected flag(s) TO 3/4 INCA [m] Description Operation Affected flag(s) TO 3/4 JMP addr Description Operation Affected flag(s) TO 3/4 MOV A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Directly jump The program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. Program Counter addr PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 1 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation
Affected flag(s)
Increment data memory Data in the specified data memory is incremented by 1 [m] [m]+1
Increment data memory and place result in the accumulator Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]+1
Move data memory to the accumulator The contents of the specified data memory are copied to the accumulator. ACC [m]
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MOV A,x Description Operation Affected flag(s) TO 3/4 MOV [m],A Description Operation Affected flag(s) TO 3/4 NOP Description Operation Affected flag(s) TO 3/4 OR A,[m] Description Operation Affected flag(s) TO 3/4 OR A,x Description Operation Affected flag(s) TO 3/4 ORM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 No operation No operation is performed. Execution continues with the next instruction. Program Counter Program Counter+1 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Move immediate data to the accumulator The 8-bit data specified by the code is loaded into the accumulator. ACC x
Move the accumulator to data memory The contents of the accumulator are copied to the specified data memory (one of the data memories). [m] ACC
Logical OR accumulator with data memory Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR [m]
Logical OR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR x
Logical OR data memory with the accumulator Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. [m] ACC OR [m]
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RET Description Operation Affected flag(s) TO 3/4 RET A,x Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Return from subroutine The program counter is restored from the stack. This is a 2-cycle instruction. Program Counter Stack
Return and place immediate data in the accumulator The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data. Program Counter Stack ACC x TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RETI Description Operation
Return from interrupt The program counter is restored from the stack, and interrupts are enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit. Program Counter Stack EMI 1 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RL [m] Description Operation
Rotate data memory left The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RLA [m] Description Operation
Rotate data memory left and place result in the accumulator Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
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RLC [m] Description Operation Rotate data memory left through carry The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 C C [m].7 TO 3/4 RLCA [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Affected flag(s)
Rotate left through carry and place result in the accumulator Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored in the accumulator but the contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 C C [m].7 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
RR [m] Description Operation
Rotate data memory right The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RRA [m] Description Operation
Rotate right and place result in the accumulator Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 [m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RRC [m] Description Operation
Rotate data memory right through carry The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 C C [m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Affected flag(s)
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RRCA [m] Description Rotate right through carry and place result in the accumulator Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is stored in the accumulator. The contents of the data memory remain unchanged. ACC.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 C C [m].0 TO 3/4 SBC A,[m] Description Operation Affected flag(s) TO 3/4 SBCM A,[m] Description Operation Affected flag(s) TO 3/4 SDZ [m] Description PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator. ACC ACC+[m]+C
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory. [m] ACC+[m]+C
Skip if decrement data memory is 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, [m] ([m]-1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
SDZA [m] Description
Decrement data memory and place result in ACC, skip if 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, ACC ([m]-1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
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SET [m] Description Operation Affected flag(s) TO 3/4 SET [m]. i Description Operation Affected flag(s) TO 3/4 SIZ [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Set data memory Each bit of the specified data memory is set to 1. [m] FFH
Set bit of data memory Bit i of the specified data memory is set to 1. [m].i 1
Skip if increment data memory is 0 The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, [m] ([m]+1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
SIZA [m] Description
Increment data memory and place result in ACC, skip if 0 The contents of the specified data memory are incremented by 1. If the result is 0, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, ACC ([m]+1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
SNZ [m].i Description
Skip if bit i of the data memory is not 0 If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
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SUB A,[m] Description Operation Affected flag(s) TO 3/4 SUBM A,[m] Description Operation Affected flag(s) TO 3/4 SUB A,x Description Operation Affected flag(s) TO 3/4 SWAP [m] Description Operation Affected flag(s) TO 3/4 SWAPA [m] Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+[m]+1
Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. [m] ACC+[m]+1
Subtract immediate data from the accumulator The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+x+1
Swap nibbles within the data memory The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged. [m].3~[m].0 [m].7~[m].4
Swap data memory and place result in the accumulator The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged. ACC.3~ACC.0 [m].7~[m].4 ACC.7~ACC.4 [m].3~[m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
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SZ [m] Description Skip if data memory is 0 If the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0 TO 3/4 SZA [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
Move data memory to ACC, skip if 0 The contents of the specified data memory are copied to the accumulator. If the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
SZ [m].i Description
Skip if bit i of the data memory is 0 If bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i=0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
TABRDC [m] Description Operation
Move the ROM code (current page) to TBLH and data memory The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
TABRDL [m] Description Operation
Move the ROM code (last page) to TBLH and data memory The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
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XOR A,[m] Description Operation Affected flag(s) TO 3/4 XORM A,[m] Description Operation Affected flag(s) TO 3/4 XOR A,x Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical XOR accumulator with data memory Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator. ACC ACC XOR [m]
Logical XOR data memory with the accumulator Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected. [m] ACC XOR [m]
Logical XOR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected. ACC ACC XOR x
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Package Information
48-pin SSOP (300mil) Outline Dimensions
48 A
25 B
1 C C'
24
G H a F
D E
Symbol A B C C D E F G H a
Dimensions in mil Min. 395 291 8 613 85 3/4 4 25 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 25 3/4 3/4 3/4 3/4 Max. 420 299 12 637 99 3/4 10 35 12 8
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48-pin LQFP (77) Outline Dimensions
C D 36 25 G H
I 37 24
F A B E 48 13 K 1 12 a J
Symbol A B C D E F G H I J K a
Dimensions in mm Min. 8.9 6.9 8.9 6.9 3/4 3/4 1.35 3/4 3/4 0.45 0.1 0 Nom. 3/4 3/4 3/4 3/4 0.5 0.2 3/4 3/4 0.1 3/4 3/4 3/4 Max. 9.1 7.1 9.1 7.1 3/4 3/4 1.45 1.6 3/4 0.75 0.2 7
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Product Tape and Reel Specifications
Reel Dimensions
T2 D
A
B
C
T1
SSOP 48W Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 3301 1000.1 13+0.5 -0.2 20.5 32.2+0.3 -0.2 38.20.2
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Carrier Tape Dimensions
D
E F W C B0
P0
P1
t
D1
P K2 A0
K1
SSOP 48W Symbol W P E F D D1 P0 P1 A0 B0 K1 K2 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 320.3 160.1 1.750.1 14.20.1 2 Min. 1.5+0.25 40.1 20.1 120.1 16.20.1 2.40.1 3.20.1 0.350.05 25.5
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Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District, Shenzhen, China 518057 Tel: 0755-8616-9908, 8616-9308 Fax: 0755-8616-9533 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 010-6641-0030, 6641-7751, 6641-7752 Fax: 010-6641-0125 Holtek Semiconductor Inc. (Chengdu Sales Office) 709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016 Tel: 028-6653-6590 Fax: 028-6653-6591 Holmate Semiconductor, Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com
Copyright O 2006 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
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